An Efficient Design Representation of Conservative Reversible Logic Gates

Abstract

Computers, which have become a ubiquitous staple of modern society, consume nearly 10% of all the energy produced worldwide. While computing implementation technology has been made more energy efficient over the years, the energy required to operate a gate logically has become an increasingly large proportion of the total energy required. A systematic improvement of this power use would result in significant power savings, which would grow even more appreciable as overall efficiency improves. One method for achieving these power savings would be the use of conservative reversible logic (CRL) gates for system design. However, to date, only a few designs using these types of gates have been developed. This sporadic development is primarily due to the lack of a systematic method for representing CRL gates. This work describes an accurate and compact design representation of CRL gates based on a known variation of a zero-suppressed binary decision diagram, called PiDD. Two methods of adapting PiDDs to represent CRL gates of any size are presented, along with examples of design manipulation and analysis.