An Efficient Method of Analyzing Conservative Reversible Logic Gates and Circuits

Abstract

Computers, which have become a ubiquitous staple of modern society, consume nearly 10% of all the energy produced worldwide. While computing implementation technology has been made more energy efficient over the years, the energy required to operate a gate logically has become an increasingly large proportion of the total energy required. A systematic improvement of this power use would result in significant power savings, which would grow even more appreciable as overall efficiency improves. One method for achieving these power savings would be the use of conservative reversible logic (CRL) gates for system design. However, to date, only a few designs using these types of gates have been developed. One of the reasons for this sporadic development is due to the lack of an efficient method of analyzing CRL gates and circuits. This work describes an accurate and efficient method for analyzing the outputs of CRL gates and circuits of any size using a modified Karnaugh Map (K-Map). The full analysis of several CRL gates and circuits are presented, along with an efficiency comparison to conventional analysis methods.